A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS
نویسندگان
چکیده
A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL’s frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm and draws 200 μA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.
منابع مشابه
Duty-Cycled PLL for Wireless Sensor Nodes in 65nm CMOS
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عنوان ژورنال:
- J. Solid-State Circuits
دوره 45 شماره
صفحات -
تاریخ انتشار 2010